? semiconductor components industries, llc, 2007 october, 2007 - rev. 12 1 publication order number: 2n5684/d 2n5684 (pnp), 2n5686 (npn) high-current complementary silicon power transistors these packages are designed for use in high-power amplifier and switching circuit applications. features ? high current capability - i c continuous = 50 amperes ? dc current gain - h fe = 15-60 @ i c = 25 adc ? low collector-emitter saturation voltage - v ce(sat) = 1.0 vdc (max) @ i c = 25 adc ? pb-free packages are available* maximum ratings (note 1) rating symbol value unit collector-emitter voltage v ceo 80 vdc collector-base voltage v cb 80 vdc emitter-base voltage v eb 5.0 vdc collector current - continuous i c 50 adc base current i b 15 adc total power dissipation @ t c = 25 c derate above 25 c p d 300 1.715 mw mw/ c operating and storage temperature range t j , t stg -65 to +200 c thermal characteristics characteristic symbol max unit thermal resistance, junction-to-case jc 0.584 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. indicates jedec registered data. 300 0 0 20 40 60 80 100 120 140 160 180 200 figure 1. power derating temperature ( c) p d , power dissipation (watts) 250 150 100 50 200 safe area curves are indicated by figure 5. all limits are applicable and must be observed. http://onsemi.com 50 ampere complementary silicon power transistors 60-80 volts, 300 watts to-204 (to-3) case 197a style 1 marking diagram 2n568x = device code x = 4 or 6 g = pb-free package a = location code yy = year ww = work week mex = country of orgin 2n568xg ayyww mex device package shipping ordering information 2n5686 to-3 100 units/tray 2N5686G to-3 (pb-free) 100 units/tray 2n5684g to-3 (pb-free) 100 units/tray *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
2n5684 (pnp), 2n5686 (npn) http://onsemi.com 2 ????????????????????????????????? ????????????????????????????????? (t c = 25 c unless otherwise noted) (note 2) ?????????????????????? ?????????????????????? characteristic ????? ????? ??? ??? ???? ???? ??? ??? ????????????????????????????????? ????????????????????????????????? ?????????????????????? ?????????????????????? collector-emitter sustaining voltage (note 3) (i c = 0.2 adc, i b = 0) ????? ????? ??? ??? ???? ???? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? ?????????????????????? ?????????????????????? ?????????????????????? c) ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? ????????????????????????????????? ????????????????????????????????? on characteristics ?????????????????????? ?????????????????????? ?????????????????????? dc current gain (note 3) (i c = 25 adc, v ce = 2.0 vdc) (i c = 50 adc, v ce = 5.0 vdc) ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?????????????????????? ?????????????????????? ?????????????????????? ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? ????????????????????????????????? ????????????????????????????????? dynamic characteristics ?????????????????????? ?????????????????????? current-gain - bandwidth product (i c = 5.0 adc, v ce = 10 vdc, f = 1.0 mhz) ????? ????? ??? ??? ???? ???? ??? ??? ?????????????????????? ?????????????????????? ?????????????????????? ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?????????????????????? ?????????????????????? ????? ????? ??? ??? ???? ???? ??? ??? 300 s, duty cycle 2.0%. figure 2. switching time test circuit 1.0 0.5 figure 3. turn-on time i c , collector current (amp) t, time (s) 0.7 0.5 0.2 0.07 0.05 0.02 0.01 0.7 1.0 2.0 3.0 5.0 7.0 10 50 t j = 25 c i c /i b = 10 v cc = 30 v 0.03 0.3 30 0.1 20 2n5684 (pnp) 2n5686 (npn) t r t d +2.0 v 0 t r 20ns -12v 10 to 100 s duty cycle 2.0% r b r l v cc -30 v to scope t r 20 ns v cc -30 v to scope t r 20 ns r l r b +10v 0 -12v 10 to 100 s duty cycle 2.0% t r 20ns v bb +4.0 v for curves of figures 3 & 6, r b & r l are varied. input levels are approximately as shown. for npn circuits, reverse all polarities.
2n5684 (pnp), 2n5686 (npn) http://onsemi.com 3 figure 4. thermal response t, time (ms) 1.0 0.01 0.02 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 r(t), effective transient thermal resistance (normalized) 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 2000 500 jc (t) = r(t) jc jc = 0.584 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 d = 0.5 0.05 0.02 0.01 single pulse 0.1 1000 0.2 100 1.0 figure 5. active-region safe operating area v ce , collector-emitter voltage (volts) 50 20 10 5.0 0.1 2.0 3.0 7.0 10 20 30 50 100 second breakdown limited bonding wire limited thermally limited @ t c = 25 c (single pulse) 70 2.0 i c , collector current (amp) t j = 200 c curves apply below rated v ceo dc 1.0 ms 500 s 1.0 0.5 0.2 5.0 100 s 5.0 ms 2n5684, 2n5686 there are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. safe operating area curves indicate i c - v ce limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. the data of figure 5 is based on t j(pk) = 200 c; t c is variable depending on conditions. second breakdown pulse limits are valid for duty cycles to 10% provided t j(pk) 200 c. t j(pk) may be calculated from the data in figure 4. at high case temperatures, thermal limitations will reduce the power that can be handled to values l ess than the limitations imposed by second breakdown. 4.0 0.5 figure 6. turn-off time i c , collector current (amp) 2.0 1.0 0.6 0.4 0.2 0.7 1.0 2.0 3.0 7.0 20 50 t j = 25 c i b1 = i b2 i c /i b = 10 v ce = 30 v 0.3 t, time (s) t s 5.0 5000 0.1 figure 7. capacitance v r , reverse voltage (volts) 500 2.0 5.0 10 20 100 50 0.2 0.5 1.0 c, capacitance (pf) 3000 1000 700 t j = 25 c 0.8 3.0 30 2000 10 2n5684 (pnp) 2n5686 (npn) t f c ib 2n5684 (pnp) 2n5686 (npn) c ob c ob c ib
2n5684 (pnp), 2n5686 (npn) http://onsemi.com 4 v ce , collector-emitter voltage (volts) v ce , collector-emitter voltage (volts) 500 0.5 figure 8. dc current gain i c , collector current (amp) 5.0 0.7 1.0 2.0 5.0 7.0 10 20 50 70 30 20 10 100 50 h fe , dc current gain t j = +150 c +25 c -55 c 7.0 200 300 v ce = 2.0 v v ce = 10 v 3.0 30 pnp 2n5684 i c , collector current (amp) h fe , dc current gain t j = +150 c +25 c -55 c v ce = 2.0 v v ce = 10 v npn 2n5686 figure 9. collector saturation region 2.0 0.1 i b , base current (amp) 0 0.2 1.0 2.0 5.0 10 0.8 0.4 i c = 10 a t j = 25 c 25 a 1.2 1.6 0.5 3.0 40 a 0.1 i b , base current (amp) 0.2 1.0 2.0 5.0 10 i c = 10 a t j = 25 c 25 a 0.5 3.0 40 a 0.3 2.5 0.5 i c , collector current (amp) 0.7 1.0 2.0 3.0 5.0 10 20 50 2.0 1.5 1.0 0.5 0 t j = 25 c v be(sat) @ i c /i b = 10 v ce(sat) @ i c /i b = 10 v, voltage (volts) figure 10. ?on? voltages 30 v be @ v ce = 2.0 v 7.0 2.0 0.5 i c , collector current (amp) 0.7 1.0 2.0 3.0 5.0 10 20 50 1.6 1.2 0.8 0.4 0 t j = 25 c v be(sat) @ i c /i b = 10 v ce(sat) @ i c /i b = 10 v, voltage (volts) 30 v be @ v ce = 2.0 v 500 0.5 5.0 0.7 1.0 2.0 5.0 7.0 10 20 50 70 30 20 10 100 50 7.0 200 300 3.0 30 2.0 0 0.8 0.4 1.2 1.6
2n5684 (pnp), 2n5686 (npn) http://onsemi.com 5 package dimensions to-204 (to-3) case 197a-05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 1: pin 1. base 2. emitter case: collector dim min max min max millimeters inches a 1.530 ref 38.86 ref b 0.990 1.050 25.15 26.67 c 0.250 0.335 6.35 8.51 d 0.057 0.063 1.45 1.60 e 0.060 0.070 1.53 1.77 g 0.430 bsc 10.92 bsc h 0.215 bsc 5.46 bsc k 0.440 0.480 11.18 12.19 l 0.665 bsc 16.89 bsc n 0.760 0.830 19.31 21.08 q 0.151 0.165 3.84 4.19 u 1.187 bsc 30.15 bsc v 0.131 0.188 3.33 4.77 a n e c k -t- seating plane 2 pl d m q m 0.30 (0.012) y m t m y m 0.25 (0.010) t -q- -y- 2 1 l g b v h u on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free usa/canada japan : on semiconductor, japan customer focus center ?2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 ? phone : 81-3-5773-3850 2n5684/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 61312, phoenix, arizona 85082-1312 usa ? phone : 480-829-7710 or 800-344-3860 toll free usa/canada ? fax : 480-829-7709 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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